About
I am a Postdoctoral Associate in the System Software Research Group (SSRG) at Virginia Tech, working with Prof. Binoy Ravindran. My research focuses on secure processor design and architecture for AI systems — spanning microcode-level memory safety enforcement, side-channel attack mitigation, and on-chip interconnects for AI accelerators.
My current work investigates architectural mechanisms for enforcing memory safety and compartmentalization below the ISA, enabling strong security guarantees without relying on compiler or operating system support. I serve as Co-Principal Investigator on an Office of Naval Research (ONR)-funded project (TrustedCPU, $986,606) advancing microcode-level security enforcement for spatial, temporal, and transient execution safety.
I completed my Ph.D. at IIT Guwahati, India, where my thesis focused on energy-efficient Network-on-Chip (NoC) design under dark silicon constraints, developing techniques to extend NVM-based router lifetime while reducing power consumption.
I am actively seeking research opportunities and collaboration in secure processor architecture and AI systems security, available from August 2026.
Research
TrustedCPU: Microcode-Based Security Enforcement★
This research focuses on microcode-level mechanisms for enforcing spatial and temporal memory safety, heap memory corruption attacks, and compartmentalization below the ISA, enabling strong security guarantees without requiring changes to compilers or operating systems. As a Co-Principal Investigator on the ONR-funded TrustedCPU project, I design architectural mechanisms that integrate security enforcement into the processor front-end and decode pipeline, providing fine-grained isolation while maintaining compatibility with existing systems.
Input-Oriented Object Compartmentalization (IOCS)
IOCS is a fully automated framework for fine-grained software compartmentalization aimed at mitigating memory corruption vulnerabilities. It combines static and dynamic taint analysis to track input-derived data and rewrites program binaries to isolate each object into dedicated memory compartments. This approach provides strong security guarantees without requiring source code modifications, manual annotations, or specialized hardware. IOCS also incorporates formal verification of the transformed binaries and demonstrates low performance overhead (~3%) in real-world applications such as Nginx.
Automated Implementation of Secure Silicon (AISS)
As part of the DARPA/Synopsys AISS program, I led multiple research efforts on secure and configurable cryptographic hardware and hardware threat analysis. My work involved the design, validation, and security evaluation of cryptographic modules including AES, RSA, ECDSA, ECIES, and SHA. I developed automated finite-state machine (FSM) encoding techniques to enhance resilience against laser fault injection attacks, achieving improved security while maintaining area efficiency; this work was published at ICCD 2022 and extended to elliptic curve cryptographic designs. In parallel, I conducted comprehensive hardware threat analysis, including hardware Trojan detection, malicious implant identification, FSM security validation, and fault injection mitigation. I also led project execution, coordinated team efforts, and contributed to secure hardware design workflows aligned with DARPA’s hardware assurance and trusted silicon objectives.
Software/Hardware Co-Design for Secure Speculative Execution
Contributed to hardware/software co-design research on mitigating speculative execution side-channel attacks (e.g., Spectre) through compiler-assisted secure execution mechanisms and gem5-based architectural modeling and evaluation, improving processor security and execution efficiency.
Publications
ML-based Flow Correlation Attack on Anonymous Routing and Lightweight Countermeasures for NoC-based SoCs
Investigating Frequency Scaling, Non-Volatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon★
Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects★
Write-Variation Aware Alternatives to Replace SRAM Buffers with Non-Volatile Buffers in On-Chip Interconnects
Microcode-level Heap Memory Attack Mitigation
IOCS: Input-Oriented Object Compartmentalization for Memory Damage Containment
Modeling and Exploration of Gain Competition Attacks in Optical Network-on-Chip Architectures
Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks★
DidaSel: Dirty Data Based Selection of VC for Effective Utilization of NVM Buffers in On-Chip Interconnects★
ZENCO: Zero-bytes Based Encoding for Non-Volatile Buffers in On-Chip Interconnects★
Write Variation Aware Non-Volatile Buffers for On-Chip Interconnects
Non-blocking Gated Buffers for Energy Efficient On-Chip Interconnects in the Era of Dark Silicon
Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors
Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors
Contact
The best way to reach me is by email at rkhushboo@vt.edu.